.module/ram flash_srv;



{
 The word ulock1_a describes the 14-bit address range for the BEAD register,
 while ulock1_c must be put into BDMAC, containing the upper 8 page bits
 shifted 8 bits left and ORed with 0x7 command bits to perfrom the BDMA write.
 i.e. the first bus cycle is address 0x5555 and 0xaa as data.
}

{ DMA Register Settings to unlock the flash }

{ Unlock Bus Cycle 1 }
.const unlock1_lo=   0x1555;	{ BEAD }
.const unlock1_hi=   0x0107;	{ Ctrl }
.const unlock1_data= 0x00AA;    { Data }

{ Unlock Bus Cycle 2 }
.const unlock2_lo=   0x2aaa;	{ BEAD }
.const unlock2_hi=   0x0007;	{ Ctrl }
.const unlock2_data= 0x0055;	{ Data }



{ Global setup for BDMA port ------------------------------------------ }

bdma_setup:
	ax0 = dm(PFTYPE);	{ set 7 wait states for BDMA access 	}
	ay0 = 0x7000;
	ar  = ax0 or ay0;
	dm(PFTYPE) = ar;

	ar = imask;
	ar = setbit 3 of ar;	{ IRQ driven writes and reads 		}
	imask= ar;		{ what the hell is that?  		}
	ena ints;

	rts;

{ Program a flash byte ------------------------------------------------ }
{ c_byte	:	 0xA0	}
{ d_byte	:	value	}
{ addr_lo	:   low 16bit	}
{ addr_hi	:    hi  6bit	}

prog_byte:
	call init_seq;		{ unlock sequence			}
	call cmd_write;		{ command word written			}

	ar  = dm(d_byte);
	dm(d_btmp) = ar;
	call calc_adr;
	call DQ7_poll;		{ check for internal completion		}

	rts;

{ Read a byte --------------------------------------------------------- }
{ d_byte	:	readback value	}
{ addr_lo	:	low 16bit	}
{ addr_hi	:	hi 16bit	}

read_byte:
	ar  = ^d_byte;
	dm(BDMA_BIAD) = ar;
	i7  = dm(addr_lo);
	dm(BDMA_BEAD) = i7;
	dm(addr_lt) = i7;		{ store for readback }
	sr1 = dm(addr_hi);
	sr  = lshift sr1 by 10 (hi);
	ar  = dm(addr_lo);
	sr  = sr or lshift ar by 10 (lo);
	ay0 = 0xff00;
	ar  = sr1 and ay0;
	ay0 = 0x0003;
	ar  = ar or ay0;
	dm(BDMA_BDMA_Ctrl) = ar;
	ar  = 0x0001;
	dm(BDMA_BWCOUNT) = ar;

	idle;
	rts;

{ Erase a sector -------------------------------------------------------- }
sector_erase:
	call init_seq;
	call cmd_write;
	call init_seq;

	ar = 0x30;
	dm(d_btmp) = ar;
	call calc_adr;
	
	call DQ7_poll;

	rts;

mem_ident:

{ Initialize Sequence --------------------------------------------------- }
init_seq:
	ar = ulock1_b;		dm(d_btmp) 		= ar;
	ar = ^d_btmp;		dm(BDMA_BIAD) 		= ar;
	ar = unlock1_lo;	dm(BDMA_BEAD) 		= ar;
	ar = unlock1_hi;	dm(BDMA_BDMA_Ctrl) 	= ar;
	ar = 0x0001;		dm(BDMA_BWCOUNT) 	= ar;

	idle;

init_seq

